1. Field of the Invention
This invention relates generally to semiconductor devices and more specifically, relates to barrier layers for device electrodes that protect the electrodes from active components in lead-free solders.
2. Description of the Prior Art
Devices such as DirectFET® type devices (see U.S. Pat. No. 6,624,522) and flip-chip type devices have one or more metallized electrodes made of aluminum for example, formed on a first surface of a semiconductor die. These electrodes are configured to be soldered directly to conductive pads on a support substrate, such as a printed circuit board, for example. Still other devices may have one or more metallized electrodes that are configured such that when the device is packaged, the electrodes are soldered either directly or indirectly to the package leads.
For example, referring to FIG. 1 and FIG. 2 there is shown a bottom view of an example DirectFET® type device package 100 (of the type disclosed in the aforementioned patent) and a cross-sectional side view of a portion of this device package as shown by circle 101a of FIG. 1. Device package 100 includes a cup-shaped or can-shaped conductive clip 112 that has an open bottom (shown in FIG. 1), a top web 113, and two flanges 114 and 115 that are electrically connected to web 113. Housed within clip 112 is a power MOSFET semiconductor die 102. Die 102 includes a drain electrode 103 on a bottom surface thereof and a source electrode 104 and a gate electrode 105 on a top surface thereof (the source and gate electrodes are represented by the dotted lines in FIG. 1). Drain electrode 103 is in electrical contact with web 113 and thereby with flanges 114 and 115. Source electrode 104 and gate electrode 105 are exposed by the open bottom of conductive clip 112 and are intended to be soldered directly to the pads of a substrate, for example.
In order to facilitate the soldering of the source and gate electrodes to the substrate pads, solderable contacts 109 and 110 are formed atop source electrode 104 and solderable contact 108 is formed atop gate electrode 105. Solderable contacts 108, 109, and 110 are typically made of a silver containing solderable metal such as a tri-metal stack of titanium 131, nickel 132, and silver 133 as shown in FIG. 2A, which is an expanded cross-sectional side view of a portion of solderable contact 110 as shown by circle 101b. A passivation layer 120 formed of epoxy for example and acting as a solder resist for example, is disposed over the top surface of die 102 and along the top surfaces of source electrode 104 and gate electrode 105. Openings 120a, 120b, and 120c are formed in passivation layer 120 over the source and gate electrodes, thereby exposing each of the solderable contacts on these electrodes.
In the past, passivation layer 120 and solderable contacts 108-110 have been formed such that the solderable contacts and passivation layer abut/overlap. However, this abutting/overlapping configuration has created device reliability issues. Specifically, it has been found that under prolonged exposure to electric fields and moisture, silver ions from the solderable contacts may migrate and form dendrites. Notably, when solder is applied to the surfaces of these contacts in order to attach the electrodes of the die to the pads of a substrate, the solder will typically dissolve the exposed silver along the contact surfaces, thereby forming a solder alloy that captures the silver and prevents the formation of dendrites. However, when the passivation layer and solderable contacts are formed in an abutting/overlapping relationship, the passivation layer conceals portions of the outer surfaces of the solderable contacts, thereby preventing the silver along these surfaces from being reached during soldering as a described above. As a result, the silver along these surfaces is not dissolved by the solder and may be a source of migrating ions, which may migrate over the passivation layer and form dendrites, reducing device reliability.
To overcome this problem, openings 120a-120c in the passivation layer may be configured to be wider than the solderable contacts 108-110, as shown in FIGS. 1 and 2. As a result, the solderable contacts 108-110 are spaced from passivation layer 120 by surrounding gaps, such as gap 121, which gaps expose the metallized electrodes thereunder, as shown in FIG. 2. With this configuration, the entire top and side surfaces of the solderable contacts 108-110 are exposed, thereby allowing the solder to cover these surfaces and dissolve the exposed silver, limiting the formation of dendrites.
Notably, however, this gapped configuration of the passivation layer and solderable contacts causes other problems. Specifically, the solders commonly used in the past to connect the solderable contacts 108-110 to the pads of a substrate were lead-containing solders. However, lead-free solders are now in use and are being developed to avoid the environmental hazards of lead. A key lead-free solder is a tin/silver/copper alloy known as “SAC”. The SAC alloys melt at a higher temperature than lead eutectic based solders used in conventional board assemblies to date. Notably, the SAC alloys contain fluxes that activate the surfaces of the solderable contacts. In particular, these fluxes may contain several acids, such as acids within the carboxylic acid group. During the solder activation stage, oxides present on the surfaces of the solderable contacts are etched by these acids to create clean surfaces onto which the solder can alloy.
Notably, during this solder activation stage, the fluxes within the solder may extend into the gaps, such as gap 121, that extend between the solderable contacts and passivation layer 120 and may contact the exposed aluminum electrodes thereunder. It has been found that the acids within these fluxes adversely react with the aluminum electrodes, causing holes to form through the electrodes. As a result, the acidic fluxes are able to attack the active semiconductor junctions and gates under the electrodes, thereby affecting the reliability of the device.
Referring to FIG. 3, there is shown an alternative cross-sectional side view of the circled portion 101a of the device package of FIG. 1. Here, a protective passivation layer 135 made of nitride or an acrylic acetate for example, has been deposited along the top surfaces of the source and gate electrodes in order to protect the electrodes and the active junctions and gates thereunder from acidic fluxes. In particular, passivation layer 135 has been deposited under passivation layer 120 and along the gaps between the solderable contacts and passivation layer 120. However, it has been found that the formation of protective layer 135 is expensive and also affects the quality of the resulting device.